;; Copyright 1987 by NeXT Inc. ;; Author - John Strawn ;; ;; Modification history ;; -------------------- ;; 11/12/87/jos - initial file created from DSPAPSRC/cvmul.asm ;; 02/23/88/jms - cosmetic changes to code and documentation ;; 03/23/88/jms - add test for cnt=0 ;; 03/29/88/jms - fix bugs in CALLING DSP PROGRAM TEMPLATE ;; ;; ------------------------------ DOCUMENTATION --------------------------- ;; NAME ;; cvadd (AP macro) - complex vector add ;; - form a complex vector from the elementwise sum of two complex vectors ;; ;; SYNOPSIS ;; include 'stdmacros' ; load standard DSP macro package ;; cvadd pf,ic,ainp10,iinp10,ainp20,iinp20,aout0,iout0,cnt0 ;; ;; MACRO ARGUMENTS ;; pf = global label prefix (any text unique to invoking macro) ;; ic = instance count (such that pf\_cvadd_\ic is globally unique) ;; sinp1 = input vector 1 memory space ('x' or 'y') ;; ainp10 = input vector 1 base address ;; iinp10 = increment for input vector 1 ;; sinp2 = input vector 2 memory space ('x' or 'y') ;; ainp20 = input vector 2 base address ;; iinp20 = increment for input vector 2 ;; sout = output vector memory space ('x' or 'y') ;; aout0 = output vector base address ;; iout0 = increment for output vector ;; cnt0 = element count ;; ;; DSP MEMORY ARGUMENTS ;; Access Description Initialization ;; ------ ----------- -------------- ;; x:(R_X)+ input vector 1 base address ainp10 ;; x:(R_X)+ input vector 1 increment iinp10 ;; x:(R_X)+ input vector 2 base address ainp20 ;; x:(R_X)+ input vector 2 increment iinp20 ;; x:(R_X)+ output vector base address aout0 ;; x:(R_X)+ output vector increment iout0 ;; x:(R_X)+ element count cnt0 ;; ;; DESCRIPTION ;; The cvadd array-processor macro computes C[k]=A[k]+B[k], where each ;; term is complex. In pseudo-C notation: ;; ;; ainp1 = x:(R_X)+; ;; iinp1 = x:(R_X)+; ;; ainp2 = x:(R_X)+; ;; iinp1 = x:(R_X)+; ;; aout = x:(R_X)+; ;; iout = x:(R_X)+; ;; cnt = x:(R_X)+; ;; ;; for (n=0;n1,Y1 move x:(R_X)+,R_I1 ; input vector 1 address move x:(R_X)+,A ; input vector 1 increment sub Y1,A x:(R_X)+,R_I2 ; input vector 2 address to R_I2 move x:(R_X)+,B ; input vector 2 increment sub Y1,B A,N_I1 ; decremented input vector 1 increment to N_I1 move x:(R_X)+,R_O ; output vector address move x:(R_X)+,A ; output vector decrement sub Y1,A B,N_I2 ; decremented input vector 2 increment to N_I2 move A,N_O ; decremented output vector increment to N_O move x:(R_X)+,A ; count ; set up loop and pipelining tst A (R_O)-N_O ; position output pointer for first "store i" jeq pf\_cvadd_\ic\_l2 ; test A to protect against count=0 move sout:(R_O),B ; prefetch item for first "store i" ; inner loop do A,pf\_cvadd_\ic\_l1 if "sinp1"=="sinp2" move sinp1:(R_I1)+,A ; fetch r1 move sinp2:(R_I2)+,X0 ; fetch r2 add X0,A B,sout:(R_O)+N_O ; store i move sinp1:(R_I1)+N_I1,B ; fetch i1 move sinp2:(R_I2)+N_I2,X1 ; fetch i2 add X1,B A,sout:(R_O)+ ; store r else if "sinp1"=='x' move sinp1:(R_I1)+,A sinp2:(R_I2)+,Y0 add Y0,A B,sout:(R_O)+N_O move sinp1:(R_I1)+N_I1,B sinp2:(R_I2)+N_I2,Y1 add Y1,B A,sout:(R_O)+ else move sinp2:(R_I2)+,X0 sinp1:(R_I1)+,A add X0,A B,sout:(R_O)+N_O move sinp2:(R_I2)+N_I2,X1 sinp1:(R_I1)+N_I1,B add X1,B A,sout:(R_O)+ endif endif pf\_cvadd_\ic\_l1 move B,sout:(R_O) ; store last i pf\_cvadd_\ic\_l2 end_mac 'cvadd' endm end_def 'cvadd'